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AND8044/D Single-Channel 1206A ChipFETt Power MOSFET Recommended Pad Pattern and Thermal Performance
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APPLICATION NOTE
INTRODUCTION New ON Semiconductor ChipFETs in the leadless 1206A package feature the same outline as popular 1206A resistors and capacitors but provide all the performance of true power semiconductor devices. The 1206A ChipFET has the same footprint as the body of the TSOP-6 and can be thought of as a leadless TSOP-6 for purposes of visualizing board area, but its thermal performance bears comparison with the much large SO-8. This technical note discusses the single-channel ChipFET 1206A pin-out, package outline, pad patterns, evaluation board layout and thermal performance. PIN-OUT Figure 1 shows the pin-out description and Pin 1 identification for the single-channel 1206A ChipFET device. The pin-out is similar to the TSOP-6 configuration, with two additional drain pins to enhance power dissipation and thermal performance. The legs of the device are very short, again helping to reduce the thermal path to the external heatsink/pcb and allowing a larger die to be fitted in the device if necessary.
STYLE 1: PIN 1. 2. 3. 4. 5. 6. 7. 8.
0.0054 sq. in. or 3.51 sq. mm. This will assist the power dissipation path away from the device (through the copper leadframe) and into the board and exterior chassis (if applicable) for the single device. The addition of a further copper area and/or the addition of vias to other board layers will enhance the performance still further. An example of this method is implemented on the Evaluation Board described in the next section (Figure 4).
80 mil 28 mil
1 2 3 18 mil 4
8 25 mil 7 6 5
26 mil 8
DRAIN DRAIN DRAIN GATE SOURCE DRAIN DRAIN DRAIN
Figure 2. Basic Pad Layout
80 mil
1
1 2 3 4 26 mil 28 mil
8 7 6 5 68 mil
Figure 1. Single 1206A ChipFET
BASIC PAD PATTERNS The basic pad layout with dimensions is shown in Figure 2. This is sufficient for low power dissipation MOSFET applications, but power semiconductor performance requires a greater copper pad area, particularly for the drain leads. The minimum recommended pad pattern, shown in Figure 3, improves the thermal area of the drain connections (pins 1, 2, 3, 6, 7, 8) while remaining within the confines of the basic footprint. The drain copper area is
Figure 3. Minimum Recommended Pad Pattern
(c) Semiconductor Components Industries, LLC, 2001
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February, 2001 - Rev.0
Publication Order Number: AN8044/D
AND8044/D
EVALUATION BOARD FOR THE SINGLE 1206A The ChipFET 1206A evaluation board measures 0.6 in by 0.5 in. Its copper pad pattern consists of an increased pad area around the six drain leads on the top-side - approximately 0.0482 sq. in. 31.1 sq. mm - and vias added through to the underside of the board, again with a maximized copper pad area of approximately the board-size dimensions. The outer package outline is for the
Front of Board CHIPFETTMt ChipFET
8-pin DIP, which will allow test sockets to be used to assist in testing. The thermal performance of the 1206A on this board has been measured with the results following on the next page. The testing included comparison with the minimum recommended footprint on the evaluation board-size pcb and the industry standard one-inch square FR4 pcb with copper on both sides of the board.
Back of Board
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Figure 4. Evaluation Board
THERMAL PERFORMANCE Junction-to-Foot Thermal Resistance (the Package Performance) Thermal performance for the 1206A ChipFET measured as junction-to-foot thermal resistance is 15_C/W typical, 20_C/W maximum for the single device. The "foot" is the drain lead of the device as it connects with the body. This is identical to the SO-8 package RJF performance, a feat made possible by shortening the leads to the point where they become only a small part of the total footprint area. Junction-to-Ambient Thermal Resistance (dependent on pcb size) The RJA typical for the single-channel 1206A ChipFET is 80_C/W steady state, compared with 68_C/W for the SO-8. Maximum ratings are 95_C/W for the 1206-8 versus 80_C/W for the SO-8. Testing To aid comparison further, Figure 5 illustrates ChipFET 1206A thermal performance on two different board sizes and three different pad patterns. The results display the
thermal performance out to steady state and produce a graphic account of how an increased copper pad area for the drain connections can enhance thermal performance. The measured steady state values of RJA for the single 1206A ChipFET are:
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NNNNNNNNNNNNNNNN NNNNNNNNNNNNNNNN NNNNNNNNNNNNNNNN NNNNNNNNNNNNNNNN NNNNNNNNNNNNNNNN NNNNNNNNNNNNNNNN NNNNNNNNNNNNNNNN NNNNNNNNNNNNNNNN
Minimum recommended pad pattern (see Figure 3) on the evaluation board size of 0.5 in. x 0.6 in.
REV. A
156_C/W 111_C/W 78_C/W The evaluation board with the pad pattern described on Figure 4 Industry standard 1 square pcb with maximum copper both sides.
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The results show that a major reduction can be made in the thermal resistance by increasing the copper drain area. In this example, a 45_C/W reduction was achieved without having to increase the size of the board. If increasing board size is an option, a further 33_C/W reduction was obtained by maximizing the copper from the drain on the larger 1 square pcb.
AND8044/D
160 THERMAL RESISTANCE (C/W) Single EVB 120 Min. Footprint 80
40 1" Square PCB 0 10-5 10-4 10-3 10-2 10-1 1 10 100 1000
TIME (Secs)
Figure 5. Single 1206A ChipFET
SUMMARY The thermal results for the single-channel 1206A ChipFET package display similar power dissipation performance to the SO-8 with a footprint reduction of 80%.
Careful design of the package has allowed for this performance to be achieved. The short leads allow the die size to be maximized and thermal resistance to be reduced within the confines of the TSOP-6 body size.
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AND8044/D
PACKAGE DIMENSIONS
ChipFET CASE 1206A-02 ISSUE B
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM PER SIDE. 4. LEADFRAME TO MOLDED BODY OFFSET IN HORIZONTAL AND VERTICAL SHALL NOT EXCEED 0.08 MM. 5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE BURRS. 6. NO MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEAD SURFACE. 7. 126A-01 OBSOLETE. NEW STANDARD IS 1206A-02. DIM A B C D G J K L M S MILLIMETERS MIN MAX 2.95 3.10 1.55 1.70 1.00 1.10 0.25 0.35 0.65 BSC 0.10 0.20 0.28 0.42 0.55 BSC 5 NOM 1.90 BSC INCHES MIN MAX 0.116 0.122 0.061 0.067 0.039 0.043 0.010 0.014 0.025 BSC 0.004 0.008 0.011 0.017 0.022 BSC 5 NOM 0.076 BSC
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8 7 6 5
M K
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C 0.05 (0.002)
ChipFET is a trademark of Vishay Siliconix.
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
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AND8044/D

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